Pixel Plane 5 renderers are Single Instruction Multiple Data (SIMD) arrays of 128x128 (16384) processors. Each processor has 208 bits of local memory and 4096 bits of additional, slower memory. All instructions are bit-serial, and an Enable register can mask out some processors from operations. Renderers are assigned to parts of the screen, often doing multiple parts serially since there are fewer renderers than regions on a screen.
In addition to the 208 bits of local memory, each processor also has 4096 bits of Backing Store, which can be accessed in 32-bit blocks. Access to this memory is significantly slower than access to the local memory, but accesses are asynchronous and can overlap other operations.
The renderers are fed SIMD instructions from the Graphics Processors, which are i860's. In this program, the i860's largely sit idle, although they might be a good source of processing power if optimizations were to be later added to the program.